spread spectrum clock generator sm562 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07022 rev. *c revised december 14, 2002 features ? 54- to 200-mhz operating frequency range wide (9) range of spread selections accepts clock and crystal inputs low power dissipation 3.3v = 165 mw. (fin = 200 mhz) frequency spread disable function center spread modulation low cycle-to cycle jitter eight-pin soic package applications high-resolution vga controllers lcd panels and monitors workstations and servers benefits peak electromagnetic interference (emi) reduction by 8 to 16 db fast time to market cost reduction block diagram pin configuration pd vco 1 8 xin/ clk xout reference divider 4 pf 8 pf 250 k feedback divider modulation control divider and mux 5 2 3 7 vdd sscc ssclk vss 4 6 lf input decoder logic s1 s0 cp 1 2 3 4 8 7 6 5 xin/clk vdd ssclk vss xout s0 s1 sscc
sm562 document #: 38-07022 rev. *c page 2 of 8 . general description the cypress sm562 is a spread spectrum clock generator (sscg) ic used for the purpose of reducing emi found in today ? s high-speed digital electronic systems. the sm562 uses a cypress proprietary phase-locked loop (pll) and spread spectrum clock (ssc) technology to synthesize and frequency modulate the input frequency of the reference clock. by frequency modulating the clock, the measured emi at the fundamental and harmonic frequencies of clock (ssclk) is greatly reduced. this reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading system performance. the sm562 is a very simple and versatile device to use. the frequency and spread% range is selected by programming s0 and s1 digital inputs. these inputs use three (3) logic states including high (h), low (l), and middle (m) logic levels to select one of the nine available frequency modulation and spread% ranges. refer to table 1 for programming details. the sm562 is intended for applications with a reference frequency in the range of 54 to 200 mhz. a wide range of digitally selectable spread percentages is made possible by using three-level (high, low and middle) logic at the s0 and s1 digital control inputs. the output spread (frequency modulation) is symmetrically centered on the input frequency. spread spectrum clock control (sscc) function enables or disables the frequency spread and is provided for easy comparison of system performance during emi testing. the sm562 is available in an eight-pin soic package with a 0 -to-70 c operating temperature range. refer to sm561 for applications with lower drive requirements and the sm560 with lower drive and frequency requirements. table 1. frequency and spread% selection (center spread) pin description pin number pin name type pin description 1xin/clki clock or crystal connection input . refer to table 1 for input frequency range selection. 2vddp positive power supply . 3gndp power supply ground . 4 ssclk o sscg modulated clock output . 5 sscc i spread spectrum clock control (enable/disable) function . sscg function is enabled when input is high and disabled when input is low. this pin is pulled high internally. 6s1i tri-level logic input control pin used to select frequency and bandwidth . see figure 1 for programming details. this pin does not have an internal pull-up or pull-down resistor. 7s0i tri-level logic input control pin used to select frequency and bandwidth . see figure 1 for programming details. this pin does not have an internal pull-up or pull-down resistor. 8xouto oscillator output pin connected to crystal . leave this pin unconnected when xin/clk is driven by an external clock source. 54? 108 mhz (low range) input frequency (mhz) s1=m s0=m s1=m s0=0 s1=1 s0=0 s1=0 s0=0 s1=0 s0=m 54 ? 60 3.6 3.1 2.6 2.1 1.8 60 ? 70 3.5 3.0 2.5 2.0 1.7 70 ? 80 3.3 2.8 2.4 1.9 1.6 80 - 100 3.0 2.5 2.1 1.7 1.4 100 - 108 2.6 2.3 1.9 1.5 1.3 108 ? 200 mhz (high range) input frequency (mhz) s1=1 s0=m s1=0 s0=1 s1=1 s0=1 s1=m s0=1 108 ? 120 2.3 1.7 1.1 0.9 120 ? 130 2.3 1.7 1.1 0.9 130 ? 140 2.3 1.7 1.1 0.9 140 ? 150 2.2 1.6 1.1 0.9 150 - 160 2.1 1.5 1.0 0.8 160 ? 170 2.0 1.5 0.9 0.8 170 - 180 1.9 1.4 0.9 0.7 180 ? 190 1.8 1.3 0.8 0.7 190 - 200 1.7 1.2 0.7 0.6 select the frequency and spread % desired and then set s1, s0 as indicated. select the frequency and spread % desired and then set s1, s0 as indicated.
sm562 document #: 38-07022 rev. *c page 3 of 8 tri-level logic with binary logic, four states can be programmed with two control lines whereas tri-level logic can program nine logic states using two control lines. tri-level logic in the sm561 is implemented by defining a third logic state in addition to the standard logic ? 1 ? and ? 0. ? pins 6 and 7 of the sm561 recognize a logic state by the voltage applied to the respective pin. these states are defined as ? 0 ? (low), ? m ? (middle), and ? 1 ? (one). each of these states has a defined voltage range that is interpreted by the sm561 as a ? 0, ? an ? m, ? or a ? 1 ? logic state. refer to table 1 for each logic state. by using two equal value resistors (typically 20k), the ? m ? state can easily be programmed. pins 6 or 7 can be tied directly to ground or v dd for logic ? 0 ? or ? 1, ? respectively. vdd = 3.3 vdc vdd = 3.3 vdc vdd = 3.3 vdc sm562 5 6 7 sm562 5 6 7 1.65 vdc 0 vdc 7 6 5 sm562 ex. 1 ex. 2 ex. 3 vdd vdd 20k 20k figure 1.
sm562 document #: 38-07022 rev. *c page 4 of 8 absolute maximum ratings [1] supply voltage (v dd ): .................................... ? 0.5v to +6.0v dc input voltage:................................... ? 0.5v to v dd + 0.5v junction temperature ................................. ? 40 c to +140 c operating temperature:...................................... 0 c to 70 c storage temperature .................................. ? 65 c to +150 c static discharge voltage(esd)........................... 2,000v ? min dc electrical characteristics v dd = 3.3v, temp. = 25 c and c l (pin 4) = 15 pf, unless otherwise noted parameter description conditions min. typ. max. unit vdd power supply range 10% 2.97 3.3 3.63 v vinh input high voltage s0 and s1 only 0.85v dd v dd v dd v vinm input middle voltage s0 and s1 only 0.40v dd 0.50v dd 0.60v dd v vinl input low voltage s0 and s1 only 0.0 0.0 0.15v dd v voh1 output high voltage ioh = 6 ma 2.4 v voh2 output high voltage ioh = 20 ma 2.0 v vol1 output low voltage ioh = 6 ma 0.4 v vol2 output low voltage ioh = 20 ma 1.2 v cin1 input capacitance xin/clk (pin 1) 3 4 5 pf cin2 input capacitance xout (pin 8) 6 8 10 pf cin2 input capacitance s0, s1, sscc (pins 7,6,5) 3 4 5 pf idd1 power supply current fin = 65 mhz, c l = 15 pf 35 45 ma idd2 power supply current fin = 200 mhz, c l = 33 pf 50 56 ma idd3 power supply current fin = 200 mhz, no load 48 54 electrical timing characteristics v dd = 3.3v, t = 25 c and c l = 15 pf, unless otherwise noted. rise/fall@ 0.4 ? 2.4v, duty@ 1.5v parameter description conditions min. typ. max. unit iclkfr input clock frequency range peak-peak = 3.0v 54 200 mhz t r clock rise time (pin 4) ssclk1, cl = 15 pf, 200 mhz 0.70 0.75 0.80 ns t f clock fall time (pin 4) ssclk1, cl = 15 pf, 200 mhz 0.70 0.75 0.80 ns t r clock rise time (pin 4) ssclk1, cl = 33 pf, 200 mhz 1.40 1.50 1.60 ns t f clock fall time (pin 4) ssclk1, cl = 33 pf, 200 mhz 1.65 1.75 1.85 ns dtyin input clock duty cycle xin/clk (pin 1) 20 50 80 % dtyout output clock duty cycle ssclk1 (pin 4) 45 50 55 % fm1 frequency modulation fin = 70 mhz 29.5 30.0 30.5 khz fm2 frequency modulation fin = 200 mhz 85.0 85.4 86.0 khz jcc1 cycle-to-cycle jitter fin = 54 mhz, mod on 150 175 ps jcc2 cycle-to-cycle jitter fin =120 mhz, mod on 175 200 ps jcc3 cycle-to-cycle jitter fin = 200 mhz, mod on 250 300 ps note: 1. single power supply: the voltage on any input or i/o pin cannot exceed the power pin during power up.
sm562 document #: 38-07022 rev. *c page 5 of 8 sscg theory of operation the sm562 is a pll-type clock generator using a proprietary cypress design to modulate the reference clock. by precisely controlling the bandwidth of the output clock, the sm562 becomes a low-emi clock generator. the theory and detailed operation of the sm562 will be discussed in the following sections. emi all digital clocks generate unwanted energy in their harmonics. conventional digital clocks are square waves with a duty cycle that is very close to 50%. because of this 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e., third, fifth, seventh, etc. it is possible to reduce the amount of energy contained in the fundamental and odd harmonics by increasing the bandwidth of the funda- mental clock frequency. conventional digital clocks have a very high q factor, which means that all of the energy at that frequency is concentrated in a very narrow bandwidth, conse- quently, higher energy peaks. regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. by reducing the peak energy at the funda- mental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for emi. conventional methods of reducing emi have been to use shielding, filtering, multilayer pcbs, etc. the sm562 reduces the peak energy in the clock by increasing the clock bandwidth, thus, lowering the q. sscg sscg uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak and cycle to cycle. the sm562 takes a narrow band digital reference clock in the range of 54 ? 200 mhz and produces a clock that sweeps between a controlled start (f1) and stop (f2) frequency at a precise rate of change. to under- stand what happens to a clock when sscg is applied, consider a 200-mhz clock with a 50% duty cycle. from a 200-mhz clock we know the following. if this clock is applied to the xin/clk pin of the sm562, the output clock at pin 4 (ssclk) will be sweeping back and forth between two frequencies. these two frequencies, f1 and f2, are used to calculate to total amount of spread or bandwidth applied to the reference clock at pin 1. as the clock is making the transition, sweep, from f1 to f2, the amount of time and sweep waveform become a very important factor in the amount of emi reduction realized from an sscg clock. the modulation domain analyzer is used to visualize the sweep waveform and sweep period. figure 2 shows the modulation profile of a 200-mhz sscg clock. notice that the actual sweep waveform is not a simple sine or sawtooth waveform. figure 2 also shows a scan of the same sscg clock using a spectrum analyzer. the spectrum analyzer scan in figure 2 shows a 10-db reduction in the peak rf energy when using the sm562 sscg clock. modulation rate spectrum spread clock generators utilize frequency modulation (fm) to distribute energy over a specific band of frequencies. the maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. the time required to transition from fmin to fmax and back to fmin is the period of the modulation rate, tmr. modulation rates of sscg clocks are generally referred to in terms of frequency or fmod = 1/tmod. the input clock frequency, fin, and the internal divider count, cdiv, determine the modulation rate. in some sscg clock generators, the selected range determines the internal divider count. in other sscg clocks, the internal divider count is fixed over the operating range of the part. the sm562 has a fixed divider count of 2332. clock frequency = fc = 200mhz clock period = tc =1/200 mhz = 5.0 ns tc = 5.0 ns 50 % 50 %
sm562 document #: 38-07022 rev. *c page 6 of 8 sm562 application schematic the schematic in figure 3 above demonstrates how the sm562 is configured in a typical application. this application is using a 200-mhz reference clock connected to pin 1. because an external reference clock is used, pin 8 (xout) is left unconnected. this configuration depicts the profile and spectrum scans shown in figure 3 . note that s0 = s1 = 1, for a spread of approximately 0.7%. device cdiv sm562 2332 (all ranges) example: device = sm562 fin = 200 mhz range = s1 = 1, s0 = 1 then; modulation rate = fmod = 200 mhz/2332 = 85.7 khz. modulation profile spectrum analyzer figure 2. sscg clock, sm562, fin = 200 mhz vdd 200 mhz reference clock n/c vdd c5 22 uf. c6 0.1 uf r5 22 application load sm562 xin/clk 1 vdd 2 gnd 3 ssclk 4 sscc 5 s1 6 s0 7 xout 8 figure 3. application schematic
sm562 document #: 38-07022 rev. *c page 7 of 8 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package drawing and dimensions all product and company names mentioned in this document are the trademarks of their respective holders. note: 2. the ordering part number differs from the marking on the actual device. ordering information [2] part number package type product flow imism562bz 8-pin soic commercial, 0 to 70 c IMISM562BZT 8-pin soic ? tape and reel commercial, 0 to 70 c marking: example: imi sm562bs date code, lot# sm562 b s package s = soic revision imi device number 8-lead (150-mil) soic s8 51-85066-a
sm562 document #: 38-07022 rev. *c page 8 of 8 document history page document title:sm562 spread spectrum clock generator document number: 38-07022 rev. ecn no. issue date orig. of change description of change ** 106950 06/06/01 ika convert from imi to cypress *a 113522 05/08/02 dmg change the marking suffix *b 119447 10/17/02 rgl corrected the values in the absolute maximum ratings to match the device. *c 122677 12/14/02 rbi added power up requirements to operating conditions information.
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